Alibaba DAMO said on March 24 that its XuanTie team will participate in the co-development of XiangShan’s next-generation Kunminghu V3 core under a new strategic cooperation announced at the 2026 XuanTie RISC-V Ecosystem Conference. The announcement matters less as a finished-chip story than as an ecosystem signal. XuanTie is Alibaba’s best-known commercial RISC-V CPU IP line, while XiangShan is China’s highest-profile open high-performance RISC-V core project. Bringing them closer suggests that China’s open RISC-V push is moving from parallel experiments toward a more coordinated alliance around server, AI and broader CPU infrastructure.
The announcement links two different kinds of RISC-V strength
The hard-news element is straightforward. At the March 24 conference, the Beijing Open Source Chip Research Institute, the Institute of Software at the Chinese Academy of Sciences and Alibaba DAMO announced a strategic cooperation, and DAMO chief scientist Meng Jianyi said XuanTie will join the co-development of XiangShan’s next-generation Kunminghu V3. That wording is important. The story is about participation in joint development, not about a taped-out processor, a shipping server chip or a completed integration between the two projects.
What gives the announcement weight is the role each side already plays inside China’s RISC-V ecosystem. XiangShan has become the country’s best-known open high-performance RISC-V core effort, while XuanTie represents Alibaba’s attempt to turn RISC-V into commercially relevant CPU IP rather than a niche academic exercise. Read together, the March 24 move looks like a coalition-building step: one side contributes an open high-performance core lineage, the other brings a commercial CPU IP program that is already being discussed in server and AI compute contexts.
XiangShan’s own documentation helps explain why the project has become so symbolic. The project says it started in 2019, has more than 4,100 GitHub stars and 550 forks, and is backed by BOSC, the Beijing Open Source Chip Research Institute, which was jointly initiated by 16 companies. For outside readers, that means XiangShan is not just a university-style research core. It already presents itself as an industrial and academic collaboration aimed at building an open high-performance processor platform.
Kunminghu already has a timeline beyond research
The Kunminghu line also comes with a development history that makes the March 24 announcement easier to read as a next-stage milestone instead of a vague partnership memo. According to background reporting cited in the source brief, the third-generation XiangShan effort was formally launched in August 2022 through a joint development program led by the Beijing Open Source Chip Research Institute together with the Institute of Computing Technology, Alibaba, Tencent, ZTE, ThunderSoft, ESWIN and Sophgo, among others. That matters because Kunminghu was designed from the beginning as a multi-party effort, not a single-lab prototype waiting for industry relevance.
The second important marker came in July 2025, when the Beijing Open Source Chip Research Institute said the third-generation Kunminghu IP core had already reached product-level delivery to its first batch of volume customers. That does not automatically prove wide commercial adoption, and the source brief correctly treats it as a milestone rather than a market-share claim. Still, first customer-grade delivery is much more concrete than a conference demo. It suggests that Kunminghu had already moved from architecture ambition to product handoff before XuanTie joined the V3 story.
Performance claims around the current Kunminghu line give the article a second layer of relevance, but they also need careful framing. TiMedia reported that Kunminghu V2 had been discussed around the 15-points-per-GHz level and positioned against Arm’s Neoverse N2 in Chinese industry coverage. Those figures are useful because they show what class of processor XiangShan wants to compete with. They should not be treated as a universal third-party audit. Even so, they help explain why a XuanTie-Kunminghu alignment is more interesting than yet another RISC-V announcement tied only to microcontrollers or edge devices.
XuanTie brings the commercial CPU-IP piece of the story
XuanTie’s own hardware ambitions make the cooperation more than symbolic. TiMedia’s RISC-V summit coverage says XuanTie C930 is aimed at server scenarios, reaches SPECint2006 performance of 15 per GHz, and integrates a dual-engine design with 512-bit RVV1.0 and 8 TOPS Matrix capability. Those are not the specs of a lightweight IoT control core. They show Alibaba is trying to position XuanTie as part of a broader push into data-center and AI-adjacent compute.
That is why XuanTie joining Kunminghu V3 changes how international readers can interpret the news. Instead of seeing China’s RISC-V efforts as isolated projects competing for attention, the March 24 announcement suggests a more layered stack could be forming: an open ISA in RISC-V, an open high-performance core project in XiangShan, commercial CPU IP through XuanTie, and industry validation through a growing group of institutional and corporate participants. In practical terms, that could make the Chinese RISC-V story easier to scale across toolchains, validation flows, server reference designs and eventually AI CPU deployment.
The broader market backdrop also helps. TiMedia, citing industry forecasts, said RISC-V SoC shipments could reach 161.81 billion units by 2030, with revenue reaching $92.7 billion. Forecasts are never guarantees, but they explain why Chinese players are trying to organize around ecosystem leverage rather than only individual chip announcements. If RISC-V is becoming a real long-cycle infrastructure market, then aligning open cores and commercial CPU IP earlier matters more than winning a single benchmark headline.
The performance headline still needs careful handling
Kunminghu V3 itself is where the opportunity and the caution meet. TiMedia’s 2025 summit coverage said Kunminghu V3 had entered the exploration stage with a target of 22 points per GHz, while the simulator was at about 20.1 points per GHz. Those numbers are strong enough to attract attention, especially because they imply XiangShan wants to move deeper into the server and AI compute conversation. But they are still target and simulator figures. They are not finished-silicon results and should not be written as such.
The same caution applies to the cooperation structure announced on March 24. The official line is that XuanTie will participate in the co-development of XiangShan’s next-generation Kunminghu V3 under a strategic cooperation. That is a meaningful escalation in ecosystem alignment, but it does not mean Alibaba and XiangShan have already unified their IP, merged their business models or completed a shared commercial roadmap. The accurate reading is deeper coordination, not completed consolidation.
What changed, and what could happen next
What changed on March 24 is that China’s open RISC-V narrative became easier to read as an alliance story instead of a collection of parallel efforts. XiangShan already had a public record of joint development starting in 2022 and first customer-grade product delivery in 2025. XuanTie already had a server-class CPU line in C930 and an ambition to move beyond embedded use cases. Putting those tracks into the same next-generation V3 effort changes the story from “another cooperation announcement” to “China is trying to make its open CPU stack more coordinated.”
What could happen next depends on whether this cooperation expands from conference signaling into shared execution. If the collaboration deepens into verification, toolchains, reference platforms and commercial partner support, China’s RISC-V push could become more legible to global customers who care about continuity, software support and product roadmaps as much as core design. If it stays mostly symbolic, then the March 24 announcement will still matter as a marker of intent, but not yet as proof of a durable competitive stack.
Either way, the strategic significance is already visible. This was not a product launch dressed up as a trend piece. It was a public sign that two of China’s most important open RISC-V camps are moving closer together at a time when the country wants RISC-V to matter in servers, AI compute and long-horizon CPU infrastructure. That shift in alignment is the real news, and the next few development cycles will show whether it becomes a stronger coalition or just a well-timed conference headline.
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Sources
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IT Home — March 24 announcement on the strategic cooperation and Kunminghu V3 participation
– https://www.ithome.com/0/931/994.htm
– Key takeaways: Confirms the March 24 strategic cooperation and the statement that XuanTie will participate in the co-development of XiangShan’s next-generation Kunminghu V3. -
XiangShan documentation — project profile and ecosystem background
– https://docs.xiangshan.cc/zh-cn/latest/
– Key takeaways: Describes XiangShan’s positioning as an open high-performance RISC-V processor project, its 2019 start, GitHub traction and BOSC-backed industrial-academic structure. -
TiMedia — 2025 RISC-V summit coverage on Kunminghu V3 and XuanTie C930
– https://www.tmtpost.com/7630986.html?rss=toutiao2
– Key takeaways: Provides the Kunminghu V3 target of 22 points per GHz, the simulator figure of 20.1, and the server-oriented framing around XuanTie C930. -
TiMedia — background on RISC-V commercialization and comparative positioning
– https://www.tmtpost.com/7604683.html?rss=toutiao2
– Key takeaways: Adds context on XuanTie C930, Kunminghu’s positioning against Arm Neoverse N2 and the broader commercialization narrative around RISC-V in China. -
IT Home — historical milestones for Kunminghu joint development and first customer delivery
– https://www.ithome.com/0/637/558.htm
– https://www.ithome.com/0/872/449.htm
– Key takeaways: Supports the August 2022 joint-development launch and the July 2025 report that Kunminghu IP had reached product-level delivery for its first batch of volume customers.
Editorial caveat: References to Kunminghu V3’s 22-points-per-GHz target and 20.1-points-per-GHz simulator figure are performance goals and pre-silicon indicators reported in media coverage, not audited shipping-chip results. The March 24 announcement should also be read as a strategic cooperation and participation commitment, not as proof of completed IP unification, tape-out or mass production.
